1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to memory cell transistor of a dynamic random access memory (DRAM) device having different source/drain junction profile connected to a direct contact (DC) node and a buried contact (BC) node.
2. Description of the Related Art
DRAM devices are generally used as a main memory of a computer system. A DRAM memory cell comprises a transistor and a capacitor. Data is stored in a memory cell by charge retention in the capacitor. If the memory cell is not periodically refreshed, the stored data will be lost due to capacitor discharge, since the capacitor is not perfectly isolated, and leakage current flows from the capacitor to surrounding coupled devices.
As DRAM devices become highly integrated, the channel length of the memory cell transistor is shortened and dosage amount in source/drain junction regions is increased; as a result, static refresh characteristics are deteriorated. To improve the static refresh characteristics, a method for controlling a depth of the source/drain junction regions has been proposed.
FIG. 1 is a cross-sectional diagram of a conventional memory cell transistor of the DRAM device having source/drain junction regions connected to a BC node and a DC node.
Referring to FIG. 1, a gate stack pattern 20 is formed as a cell transistor on a semiconductor substrate 10. The gate stack pattern 20 comprises a gate electrode having a gate insulating layer 12, a polysilicon layer 14, a silicide layer 16, and a capping insulating layer 18. Generally, the gate electrode is used as a word line. Both lateral sides of the gate stack pattern 20 have spacers 26 having an oxide layer 22 and a nitride layer 24. Source/drain junction regions 32 are formed substantially under the spacers 26. Each of the source/drain junction regions 32 includes a source/drain ion injection region 28 and a plug ion injection region 30. One of the source/drain junction regions 32 is used as a direct contact (DC) node electrically connected to a bit line and the other one is used as a buried contact (BC) node electrically connected to a storage electrode of a capacitor.
The plug ion injection region 30 is made deeper than the source/drain ion injection region 28 to reduce junction leakage for improving static refresh characteristics. The plug ion injection region 30 is generally formed from phosphorous (P) which has a lower threshold voltage. A low threshold voltage means inferior dynamic refresh characteristics.
Therefore, it is desirable to provide a memory cell transistor of a DRAM device having improved dynamic refresh characteristics as well as static refresh characteristics.